Digital readout integrated circuits (DROICs) with digital storage have immensely increased charge handling capacities compared to analog counterparts. This makes them suitable for high flux/low frame rate imaging applications. The performance of such readouts is reduced due to the quantization noise being dominant as the flux is reduced or the frame rates are increased. Various applications require high frame rate such as missile approach warning systems or airborne imaging applications. Other imaging applications that incorporate LWIR sensors require high storage capacity as the background flux is high compared to the signal to be detected. For such applications pixels with low incident photon flux levels have poor SNR reducing the quality of the image.
A digital readout with high charge handling capacity that is also capable of detecting low flux level with a high SNR is possible only by reducing the quantization noise. In order to reduce the quantization noise, smaller step sizes must be taken, which has a limit due to non-idealities of the CMOS process. The smaller the step size, which is a voltage on a storage capacitor, the higher becomes the non-idealities, which are charge injection or clock feed through errors due to switching. Moreover, capacitors cannot be made arbitrarily small, capacitors will be limited to the parasitic capacitance of the comparator node. In addition to this, in order to increase the signal to noise ratio (SNR), one has to increase the comparator reference voltage. This also contradicts to the conventional way of reducing the packet size for low quantization noise in terms of system SNR performance.
Hence reducing only the step size would not solve the quantization noise problem, without creating new ones. What is required is an effectively smaller step size, while not reducing the component sizes dramatically or if possible not at all. This can be achieved through extended counting.
Various techniques for analog to digital conversion have been proposed and applied among which are ADC per chip, ADC per column or ADC per pixel. Among all three, this invention focuses on the ADC per pixel architecture, since it reduces the requirements of the ADC, allows larger charge handling capacity as well as wide dynamic range and with the advances of silicon manufacturing technology, is becoming more attractive. The improved dynamic range means higher bit resolution with reduced step sizes, which in return results a lower quantization noise floor, hence a high SNR.
Various circuit solutions and readout methods have been proposed in the past. In the U.S. Pat. No. 8,022,350, a readout with exponentially increasing integration times have been proposed. The claimed readout increases the dynamic range, however, has limited charge storage capacity. The claimed invention uses the digital sign as end of integration and scales the output voltage with respect to the time data stored in the memory. The invention also claims the advantage of no quantization noise, which is due to not performing any ADC conversion. The implementation of the subject disclosure is different to the proposed invention as the output is analog, rather than digital.
In the U.S. Pat. No. 7,973,846 a digital readout with one bit threshold indicator and a voltage ramp is claimed. In this application, whenever the voltage threshold of the comparator is crossed, a 1 bit threshold data is sent out the pixel and the digital data corresponding to the timing of crossing is stored at the memory. An N×M×(k+1) bits of memory that is out of the pixel area is required. The technical teaching of the disclosure in question is different than that of the present invention due its limited charge handling capacity and out of pixel memory. No method to reduce quantization noise is applied.
Another approach that uses both analog and digital information out of the pixel is claimed in U.S. Pat. No. 7,795,650. The technique is applied specifically to vertically integrated sensor arrays (VISA). The disclosure presented in the '650 publication uses the asynchronous self reset with residue readout. It however has analog residue at pixel level, which is to be converted once more either on column level or chip level. The technical teaching therein differs from the present invention with its requirement of additional column based ADCs for the residue conversion and off chip (visa) memory.
A single chip solution similar to '650 patent has been claimed in the US Patent application US2010/0194956. The pixel circuit drives a digital bus fed by a comparator checking the voltage on the integration capacitor to be above the threshold level. At the end of the integration time, the residue is read to the analog bus and is converted by a column based ADC. Again the invention disclosed in the subject publication is different to the present invention by its—on-chip—column ADCs.
In the U.S. Pat. No. 6,927,796 instead of counting the residue, an estimation method is claimed with multiple non-destructive samples. The readout circuit incorporates a comparator and self reset mechanism (asynchronous self reset). At certain time instances, that is determined by the noise, various noise sources as well as a required SNR, multiple samples are quantized and the photocurrent is estimated.
The circuit implementation demonstrates a different method used to estimate the photocurrent from multiple samples, as opposed to the single sample value of the present invention.
Similar to '796 patent, in U.S. Pat. No. 7,492,400 an estimation method is used to capture multiple samples and determine the photocurrent. In this invention the method of ADC conversion is different than that of '796 patent. The ADC is shared between different pixels, to make the fine quantization followed by a coarse quantization by the comparator. Again the memory requirement is high and SNR at the high end is limited. In this disclosure, superior performance to the extended counting method is reported. This is due to the comparator offset of the extended counting method, which can be neglected when a non-uniformity correction is applied, which is usually the case especially at the IR FPAs (Focal Plane Arrays).
In another patent application, US2010/0226495, a digital readout method and apparatus is claimed. The application claims the use of both reset to voltage and charges subtract methods for synchronous readout. In an illustrative embodiment, extended counting is applied for reduced power consumption. Two charge/discharge paths to the integration capacitor that are an integer multiple to each other are used for the fine quantization phase. The approach of the invention is disadvantageous in terms of the increased non-uniformity, and in that accurate current references of sub-nano amperes are required which are hard to implement in a small pixel area. The proposed invention does not require any current or packet references, which are indeed required to be very accurate.
In another application reported in the literature with papers “A 25 μm pitch LWIR staring focal plane array with pixel-level 15-bit ADC ROIC achieving 2 mK NETD”, S. Bisotto, et all, in the Proceedings of SPIE and “A 25 μm pitch LWIR focal plane array with pixel-level 15-bit ADC providing high well capacity and targeting 2 mK NETD”, Fabrice Guellec, et all, also in the Proceedings of SPIE, digital readouts with asynchronous reset have been reported. However the reported work has high quantization noise due the packet sizes being very coarse.
Another publicly available example of a pulse modulated DROIC has been shown by Sofradir EC, Inc. in 2010, a well known leading company in FPA and infrared imaging modules in Europe. The circuit architecture thereof reveals the key properties such that a charge up to 3Ge- is handled and an NEDT (noise equivalent differential temperature) of 2 mK is achieved with an ADC resolution of 15 bits. However if the same readout topology is to be used for a MAW (missile approach warning) the readout should have a high frame rate requirement (typically around 800 Hz), so that the imaging will be fast and an integration as large as around 1 Ge- will not be the case but only around 75 Me-. In this scenario with the flux levels being low, or the frame rate requirements high, one should come up with a solution to reduce the quantization noise in order to operate closer to the shot noise limit.
The present invention is superior to the prior art by couple of points. Primarily, the invention offers a reduced quantization noise, while having the benefit of large charge handling capacity. This is achieved by extended counting at the pixel level ADC. The methodology of the present invention is advantageous compared to the prior art in reducing the circuit size and relaxing the circuit requirements. Extended counting is achieved through extended integration and this requires no additional circuit at the detector-readout interface. Compared to other inventions in the technical field, the present method is also advantageous in terms of its memory requirement or additional column based ADCs.
Further, the present invention improves the linearity of digital readouts. The charge that is supposed to be integrated, but rather has been reset during the reset operation, causes non-linearity. The present invention removes this non-linearity through a temporary storage switch at the pixel level.
Third the proposed invention improves the uniformity performance as well. The reset duration of two comparators will not be identical and will result in non-uniformity even if for two pixels of same photocurrent. The present invention removes this non-uniformity through a temporary storage switch at the pixel level.